Published by Kathy Twietmeyer on

Kazan Networks is seeking a new graduate ASIC Design Engineer with excellent analytical and technical skills for design and verification of next generation storage networking ASICs. This is an excellent opportunity to be part of a startup company

US Citizens or Permanent Residents only, and direct job applications only, please.


  • Recent Bachelor’s or Master’s degree in Electrical or Computer Engineering
  • Solid understanding of Digital Design fundamentals, and Computer Architecture
  • Proficiency with Verilog & System Verilog RTL coding and verification
  • Familiar with constrained random verification methodology (UVM) concepts
  • Good Programming/Scripting skills with languages such as Python, TCL, and BASH
  • Problem solving skills and out-of-the-box thinking
  • Strong communication skills, both verbal and written
  • Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
  • Experience with RTL Linting, Synthesis, Static Timing and logical equivalency checking (desired)
  • Strong FPGA platform based development and testing experience (desired)
  • Protocol knowledge in one or more of the following areas: TCP/IP, SCSI, Fibre Channel, Ethernet, SAS, SATA, RDMA protocols, PCIe (desired)
  • Experience with embedded CPUs, e.g. ARM (desired)


  • Micro-architecture and documentation
  • RTL coding
  • RTL verification
  • System testing and debug using FPGAs
  • FPGA builds
  • Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
  • Scripting
  • Linting, synthesis, static timing
  • Test plan documentation
Job Type: Full Time
Job Location: Roseville-CA

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