ASIC VERIFICATION ENGINEER

Published by Kathy Twietmeyer on

Position Type: Full-time

Location: Roseville, California

Kazan Networks is seeking a new graduate ASIC Verification Engineer with excellent analytical and technical skills for the verification of next generation storage networking ASICs. This is an excellent opportunity to be part of a startup company.

US Citizens or Permanent Residents only, and direct job applications only, please.

Requirements

  • Recent Bachelor’s or Master’s degree in Electrical or Computer Engineering
  • Solid understanding of Digital Design fundamentals, and Computer Architecture
  • Proficiency with Verilog & System Verilog RTL coding and verification
  • Good Programming/Scripting skills with languages such as Python, Awk & Perl
  • Good knowledge of Object-Oriented Programming
  • Problem solving skills and out-of-the-box thinking
  • Strong communication skills, both verbal and written
  • Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
  • Familiar with constrained random verification methodology (UVM) (desired)
  • Familiar with Code Coverage (desired)
  • Familiar with Functional Coverage (desired)
  • Knowledge of Assertion based Verification using System Verilog Assertions (desired)
  • Protocol knowledge in one or more of the following areas: TCP/IP, SCSI, Fiber Channel, Ethernet, SAS, SATA, RDMA protocols, PCIe (desired)
  • Experience with embedded CPUs, e.g. ARM (desired)

Responsibilities

  • RTL verification
  • Simulation Test Implementation
  • Simulation Debugging
  • Scripting
  • Test plan documentation
Job Category: ASIC DESIGN ENGINEER
Job Type: Full Time
Job Location: Roseville-CA

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